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document no. e1545e20 (ver. 2.0) date published november 2009 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2009 preliminary data sheet 4gb ddr3 sdram so-dimm ebj41uf8bas0 (512m words 64 bits, 2 ranks) specifications ? density: 4gb ? organization ? 512m words 64 bits, 2 ranks ? mounting 16 pieces of 2g bits ddr3 sdram sealed in fbga ? package: 204-pin socket type small outline dual in line memory module (so-dimm) ? pcb height: 30.0mm ? lead pitch: 0.6mm ? lead-free (rohs compliant) and halogen-free ? power supply: vdd = 1.5v 0.075v ? data rate: 1600mbps/1333mbps/1066mbps (max.) ? eight internal banks for concurrent operation (components) ? interface: sstl_15 ? burst lengths (bl): 8 and 4 with burst chop (bc) ? /cas latency (cl): 6, 7, 8, 9, 10, 11 ? /cas write latency (cwl): 5, 6, 7, 8 ? precharge: auto precharge option for each burst access ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc + 85 c 3.9 s at + 85 c < tc + 95 c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture; two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die-termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for temperature read out ? zq calibration for dq drive and odt ? programmable partial array self-refresh (pasr) ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? programmable output driver impedance control
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 2 ordering information part number data rate mbps (max.) component jedec speed bin (cl-trcd-trp) package contact pad mounted devices ebj41uf8bas0-gn-f 1600 ddr3-1600k (11-11-11) gold edj2108base-gn-f ebj41uf8bas0-dj-f 1333 ddr3-1333h (9-9-9) edj2108base-gn-f edj2108base-dj-f EBJ41UF8BAS0-AE-F 1066 ddr3-1066f (7-7-7) 204-pin so-dimm (lead-free and halogen-free) edj2108base-gn-f edj2108base-dj-f edj2108base-ae-f
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 3 pin configurations 1 pin 2 pin front side back side 71 pin 72 pin 73 pin 74 pin 203 pin 204 pin front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vrefdq 103 /ck0 2 vss 104 /ck1 3 vss 105 vdd 4 dq4 106 vdd 5 dq0 107 a10 (ap) 6 dq5 108 ba1 7 dq1 109 ba0 8 vss 110 /ras 9 vss 111 vdd 10 /dqs0 112 vdd 11 dm0 113 /we 12 dqs0 114 /cs0 13 vss 115 /cas 14 vss 116 odt0 15 dq2 117 vdd 16 dq6 118 vdd 17 dq3 119 a13 18 dq7 120 odt1 19 vss 121 /cs1 20 vss 122 nc 21 dq8 123 vdd 22 dq12 124 vdd 23 dq9 125 nc 24 dq13 126 vrefca 25 vss 127 vss 26 vss 128 vss 27 /dqs1 129 dq32 28 dm1 130 dq36 29 dqs1 131 dq33 30 /reset 132 dq37 31 vss 133 vss 32 vss 134 vss 33 dq10 135 /dqs4 34 dq14 136 dm4 35 dq11 137 dqs4 36 dq15 138 vss 37 vss 139 vss 38 vss 140 dq38 39 dq16 141 dq34 40 dq20 142 dq39 41 dq17 143 dq35 42 dq21 144 vss 43 vss 145 vss 44 vss 146 dq44 45 /dqs2 147 dq40 46 dm2 148 dq45 47 dqs2 149 dq41 48 vss 150 vss 49 vss 151 vss 50 dq22 152 /dqs5 51 dq18 153 dm5 52 dq23 154 dqs5 53 dq19 155 vss 54 vss 156 vss 55 vss 157 dq42 56 dq28 158 dq46 57 dq24 159 dq43 58 dq29 160 dq47 59 dq25 161 vss 60 vss 162 vss 61 vss 163 dq48 62 /dqs3 164 dq52 63 dm3 165 dq49 64 dqs3 166 dq53 65 vss 167 vss 66 vss 168 vss 67 dq26 169 /dqs6 68 dq30 170 dm6
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 4 front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 69 dq27 171 dqs6 70 dq31 172 vss 71 vss 173 vss 72 vss 174 dq54 73 cke0 175 dq50 74 cke1 176 dq55 75 vdd 177 dq51 76 vdd 178 vss 77 nc 179 vss 78 nc 180 dq60 79 ba2 181 dq56 80 a14 182 dq61 81 vdd 183 dq57 82 vdd 184 vss 83 a12 (/bc) 185 vss 84 a11 186 /dqs7 85 a9 187 dm7 86 a7 188 dqs7 87 vdd 189 vss 88 vdd 190 vss 89 a8 191 dq58 90 a6 192 dq62 91 a5 193 dq59 92 a4 194 dq63 93 vdd 195 vss 94 vdd 196 vss 95 a3 197 sa0 96 a2 198 nc 97 a1 199 vddspd 98 a0 200 sda 99 vdd 201 sa1 100 vdd 202 scl 101 ck0 203 vtt 102 ck1 204 vtt
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 5 pin description pin name function a0 to a14 address input row address a0 to a14 column address a0 to a9 a10 (ap) auto precharge a12 (/bc) burst chop ba0, ba1, ba2 bank select address dq0 to dq63 data input/output /ras row address strobe command /cas column address strobe command /we write enable /cs0, /cs1 chip select cke0, cke1 clock enable ck0, ck1 clock input /ck0, /ck1 differential clock input dqs0 to dqs7, /dqs0 to /dqs7 input and output data strobe dm0 to dm7 input mask scl clock input for serial pd sda data input/output for serial pd sa0, sa1 serial address input vdd power for internal circuit vddspd power for serial eeprom vrefca reference voltage for ca vrefdq reference voltage for dq vss ground vtt i/o termination supply for sdram /reset set dram to known state odt0, odt1 odt control nc no connection
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 6 serial pd matrix byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of serial pd bytes written/spd device size/crc coverage -gn 0 0 0 0 0 0 0 0 00h tbd -dj, -ae 1 0 0 1 0 0 1 0 92h 176/256/0-116 1 spd revision 0 0 0 1 0 0 0 0 10h revision 1.0 2 key byte/dram device type 0 0 0 0 1 0 1 1 0bh ddr3 sdram 3 key byte/module type 0 0 0 0 0 0 1 1 03h so-dimm 4 sdram density and banks 0 0 0 0 0 0 1 1 03h 2g bits, 8 banks 5 sdram addressing 0 0 0 1 1 0 0 1 19h 15 rows, 10 columns 6 module nominal voltage, vdd 0 0 0 0 0 0 0 0 00h 1.5v 7 module organization 0 0 0 0 1 0 0 1 09h 2 ranks/ 8 bits 8 module memory bus width 0 0 0 0 0 0 1 1 03h 64 bits/non-ecc 9 fine timebase (ftb) dividend/divi sor 0 1 0 1 0 0 1 0 52h 5/2 10 medium timebase (mtb) di vidend 0 0 0 0 0 0 0 1 01h 1 11 medium timebase (mtb) divi sor 0 0 0 0 1 0 0 0 08h 8 12 sdram minimum cycle time (tck (min.)) -gn 0 0 0 0 0 0 0 0 00h tbd -dj 0 0 0 0 1 1 0 0 0ch 1.5ns -ae 0 0 0 0 1 1 1 1 0fh 1.875ns 13 reserved 0 0 0 0 0 0 0 0 00h ? 14 sdram /cas latencies supported, lsb -gn 0 0 0 0 0 0 0 0 00h tbd - dj 0 0 1 1 1 1 0 0 3ch cl = 6, 7, 8, 9 -ae 0 0 0 1 1 1 0 0 1ch cl = 6, 7, 8 15 sdram /cas latencies supported, msb 0 0 0 0 0 0 0 0 00h ? 16 sdram minimum /cas latencies time (taa (min.)) 0 1 1 0 1 0 0 1 69h 13.125ns 17 sdram write recovery time (twr (min)) 0 1 1 1 1 0 0 0 78h 15ns 18 sdram minimum /ras to /cas delay (trcd) 0 1 1 0 1 0 0 1 69h 13.125ns 19 sdram minimum row active to row active delay (trrd) -gn 0 0 0 0 0 0 0 0 00h tbd -dj 0 0 1 1 0 0 0 0 30h 6ns -ae 0 0 1 1 1 1 0 0 3ch 7.5ns 20 sdram minimum row precharge time (trp) 0 1 1 0 1 0 0 1 69h 13.125ns 21 sdram upper nibbles for tras and trc 0 0 0 1 0 0 0 1 11h 22 sdram minimum active to precharge time (tras), lsb -gn 0 0 0 0 0 0 0 0 00h tbd -dj 0 0 1 0 0 0 0 0 20h 36ns -ae 0 0 1 0 1 1 0 0 2ch 37.5ns
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 23 sdram minimum active to active /auto- refresh time (trc), lsb -gn 0 0 0 0 0 0 0 0 00h tbd -dj 1 0 0 0 1 0 0 1 89h 49.125ns -ae 1 0 0 1 0 1 0 1 95h 50.625ns 24 sdram minimum refresh recovery time delay (trfc), lsb 0 0 0 0 0 0 0 0 00h 160ns 25 sdram minimum refresh recovery time delay (trfc), msb 0 0 0 0 0 1 0 1 05h 160ns 26 sdram minimum internal write to read command delay (twtr) 0 0 1 1 1 1 0 0 3ch 7.5ns 27 sdram minimum internal read to precharge command delay (trtp) 0 0 1 1 1 1 0 0 3ch 7.5ns 28 upper nibble for tfaw -gn 0 0 0 0 0 0 0 0 00h tbd -dj 0 0 0 0 0 0 0 0 00h 30.0ns -ae 0 0 0 0 0 0 0 1 01h 37.5ns 29 minimum four activate window delay time (tfaw) -gn 0 0 0 0 0 0 0 0 00h tbd -dj 1 1 1 1 0 0 0 0 f0h 30.0ns -ae 0 0 1 0 1 1 0 0 2ch 37.5ns 30 sdram output drivers supported 1 0 0 0 0 0 1 1 83h dll-off/rzq/6, 7 31 sdram refresh options 1 0 0 0 0 0 0 1 81h pasr/2x refresh at + 85c to + 95c 32 module thermal sensor 0 0 0 0 0 0 0 0 00h not incorporated 33 sdram device type 0 0 0 0 0 0 0 0 00h standard 34 to 59 reserved 0 0 0 0 0 0 0 0 00h ? 60 module nominal height 0 0 0 0 1 1 1 1 0fh 29 < height 30mm 61 module maximum thickness 0 0 0 1 0 0 0 1 11h 62 reference raw card used 0 1 0 0 0 1 0 1 45h raw card f2 63 address mapping from edge connecter to dram 0 0 0 0 0 0 0 0 00h standard 64 to 116 module specific section 0 0 0 0 0 0 0 0 00h ? 117 module id: manufacturer?s jedec id code, lsb 0 0 0 0 0 0 1 0 02h elpida memory 118 module id: manufacturer?s jedec id code, msb 1 1 1 1 1 1 1 0 feh elpida memory 119 module id: manufacturing location 120 module id: manufacturing date year code (bcd) 121 module id: manufacturing date week code (bcd) 122 to 125 module id: module serial number 126 cyclical redundancy code (crc) -gn 0 0 0 0 0 0 0 0 00h tbd -dj 0 1 0 0 1 0 0 1 49h -ae 0 0 0 0 1 0 1 1 0bh
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 8 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 127 cyclical redundancy code (crc) -gn 0 0 0 0 0 0 0 0 00h tbd -dj 1 0 0 1 1 0 1 0 9ah -ae 0 0 1 1 0 0 1 1 33h 128 module part number 0 1 0 0 0 1 0 1 45h e 129 module part number 0 1 0 0 0 0 1 0 42h b 130 module part number 0 1 0 0 1 0 1 0 4ah j 131 module part number 0 0 1 1 0 1 0 0 34h 4 132 module part number 0 0 1 1 0 0 0 1 31h 1 133 module part number 0 1 0 1 0 1 0 1 55h u 134 module part number 0 1 0 0 0 1 1 0 46h f 135 module part number 0 0 1 1 1 0 0 0 38h 8 136 module part number 0 1 0 0 0 0 1 0 42h b 137 module part number 0 1 0 0 0 0 0 1 41h a 138 module part number 0 1 0 1 0 0 1 1 53h s 139 module part number 0 0 1 1 0 0 0 0 30h 0 140 module part number 0 0 1 0 1 1 0 1 2dh ? 141 module part number -gn 0 1 0 0 0 1 1 1 47h g -dj 0 1 0 0 0 1 0 0 44h d -ae 0 1 0 0 0 0 0 1 41h a 142 module part number -gn 0 1 0 0 1 1 1 0 4eh n -dj 0 1 0 0 1 0 1 0 4ah j -ae 0 1 0 0 0 1 0 1 45h e 143 module part number 0 0 1 0 1 1 0 1 2dh ? 144 module part number 0 1 0 0 0 1 1 0 46h f 145 module part number 0 0 1 0 0 0 0 0 20h (space) 146 module revision code 0 0 1 1 0 0 0 0 30h initial 147 module revision code 0 0 1 0 0 0 0 0 20h (space) 148 sdram manufacturer?s jedec id code, lsb 0 0 0 0 0 0 1 0 02h elpida memory 149 sdram manufacturer?s jedec id code, msb 1 1 1 1 1 1 1 0 feh elpida memory 150 to 175 manufacturer's specific data 176 to 254 intel extreme memory profile -gn tbd -dj, -ae 0 0 0 0 0 0 0 0 00h not supported 255 open for customer use
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 9 spd for intel extreme memory profile (ebj41uf8bas0-gn) byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 176 intel extreme memory profile id string 0 0 0 0 0 0 0 0 00h tbd 177 intel extreme memory profile id string 0 0 0 0 0 0 0 0 00h tbd 178 intel extreme memory profile organization type 0 0 0 0 0 0 0 0 00h tbd 179 intel extreme memory profile revision 0 0 0 0 0 0 0 0 00h tbd 180 medium timebase (mtb) dividend for profile 1 0 0 0 0 0 0 0 0 00h tbd 181 medium timebase (mtb) divisor for profile 1 0 0 0 0 0 0 0 0 00h tbd 182 medium timebase (mtb) dividend for profile 2 0 0 0 0 0 0 0 0 00h tbd 183 medium timebase (mtb) divisor for profile 2 0 0 0 0 0 0 0 0 00h tbd 184 reserved for global byte 0 0 0 0 0 0 0 0 00h tbd [for profile 1] byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 185 module vdd voltage level 0 0 0 0 0 0 0 0 00h tbd 186 sdram minimum cycle time (tck (min.)) 0 0 0 0 0 0 0 0 00h tbd 187 sdram minimum /cas latencies time (taa (min.)) 0 0 0 0 0 0 0 0 00h tbd 188 sdram /cas latencies supported, lsb (cl mask) 0 0 0 0 0 0 0 0 00h tbd 189 sdram /cas latencies supported, msb (cl mask) 0 0 0 0 0 0 0 0 00h tbd 190 minimum cas write latency time (tcwl(min)) 0 0 0 0 0 0 0 0 00h tbd 191 sdram minimum row precharge time (trp) 0 0 0 0 0 0 0 0 00h tbd 192 sdram minimum /ras to /cas delay (trcd) 0 0 0 0 0 0 0 0 00h tbd 193 sdram write recovery time (twr (min)) 0 0 0 0 0 0 0 0 00h tbd 194 sdram upper nibbles for tras and trc 0 0 0 0 0 0 0 0 00h tbd 195 sdram minimum active to precharge time (tras), lsb 0 0 0 0 0 0 0 0 00h tbd 196 sdram minimum active to active /auto- refresh time (trc), lsb 0 0 0 0 0 0 0 0 00h tbd 197 maximum average periodic refresh interval (trefi), lsb 0 0 0 0 0 0 0 0 00h tbd 198 maximum average periodic refresh interval (trefi), msb 0 0 0 0 0 0 0 0 00h tbd 199 sdram minimum refresh recovery time delay (trfc), lsb 0 0 0 0 0 0 0 0 00h tbd 200 sdram minimum refresh recovery time delay (trfc), msb 0 0 0 0 0 0 0 0 00h tbd 201 sdram minimum internal read to precharge command delay (trtp) 0 0 0 0 0 0 0 0 00h tbd
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 10 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 202 sdram minimum row active to row active delay (trrd) 0 0 0 0 0 0 0 0 00h tbd 203 upper nibble for tfaw 0 0 0 0 0 0 0 0 00h tbd 204 minimum four activate window delay time (tfaw) 0 0 0 0 0 0 0 0 00h tbd 205 sdram minimum internal write to read command delay (twtr) 0 0 0 0 0 0 0 0 00h tbd 206 write to read & read to write command turn-around time pull-in 0 0 0 0 0 0 0 0 00h tbd 207 back to back command turn-around time pull-in 0 0 0 0 0 0 0 0 00h tbd 208 system address/ command rate (1n or 2n mode) 0 0 0 0 0 0 0 0 00h tbd 209 auto self-refresh performance (sub 1x refresh and idd6 impacts) 0 0 0 0 0 0 0 0 00h tbd 210 to 218 reserved 0 0 0 0 0 0 0 0 00h 219 vendor personality byte 0 0 0 0 0 0 0 0 00h [for profile 2] byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 220 module vdd voltage level (extreme settings) 0 0 0 0 0 0 0 0 00h tbd 221 sdram minimum cycle time (tck (min)) 0 0 0 0 0 0 0 0 00h tbd 222 minimum cas latency time (taa (min)) 0 0 0 0 0 0 0 0 00h tbd 223 sdram /cas latencies supported, lsb (cl mask) 0 0 0 0 0 0 0 0 00h tbd 224 sdram /cas latencies supported, msb (cl mask) 0 0 0 0 0 0 0 0 00h 225 minimum cas write latency time (tcwl (min)) 0 0 0 0 0 0 0 0 00h tbd 226 sdram minimum row precharge time (trp) 0 0 0 0 0 0 0 0 00h tbd 227 sdram minimum /ras to /cas delay (trcd) 0 0 0 0 0 0 0 0 00h tbd 228 sdram write recovery time (twr (min)) 0 0 0 0 0 0 0 0 00h tbd 229 sdram upper nibbles for tras and trc 0 0 0 0 0 0 0 0 00h tbd 230 sdram minimum active to precharge time (tras), lsb 0 0 0 0 0 0 0 0 00h tbd 231 sdram minimum active to active /auto- refresh time (trc), lsb 0 0 0 0 0 0 0 0 00h tbd 232 maximum average periodic refresh interval (trefi), lsb 0 0 0 0 0 0 0 0 00h tbd 233 maximum average periodic refresh interval (trefi), msb 0 0 0 0 0 0 0 0 00h tbd 234 sdram minimum refresh recovery time delay (trfc), lsb 0 0 0 0 0 0 0 0 00h tbd 235 sdram minimum refresh recovery time delay (trfc), msb 0 0 0 0 0 0 0 0 00h tbd 236 sdram minimum internal read to precharge command delay (trtp) 0 0 0 0 0 0 0 0 00h tbd 237 sdram minimum row active to row active delay (trrd) 0 0 0 0 0 0 0 0 00h tbd
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 11 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 238 upper nibble for tfaw 0 0 0 0 0 0 0 0 00h tbd 239 minimum four activate window delay time (tfaw) 0 0 0 0 0 0 0 0 00h tbd 240 sdram minimum internal write to read command delay (twtr) 0 0 0 0 0 0 0 0 00h tbd 241 write to read & read to write command turn-around time pull-in 0 0 0 0 0 0 0 0 00h tbd 242 back to back command turn-around time pull-in 0 0 0 0 0 0 0 0 00h tbd 243 system address/ command rate (1n or 2n mode) 0 0 0 0 0 0 0 0 00h tbd 244 auto self-refresh performance (sub 1x refresh and idd6 impacts) 0 0 0 0 0 0 0 0 00h tbd 245 to 253 reserved 0 0 0 0 0 0 0 0 00h 254 vendor personality byte 0 0 0 0 0 0 0 0 00h
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 12 block diagram vtt vdd vtt vdd dqs3 /dqs3 dm3 8 dq24 to dq31 dqs1 /dqs1 dm1 8 dq8 to dq15 dqs0 /dqs0 dm0 8 dq0 to dq7 dqs2 /dqs2 dm2 8 8 8 8 8 dq16 to dq23 dqs4 /dqs4 dm4 dq32 to dq39 dqs6 /dqs6 dm6 dq48 to dq55 dqs7 /dqs7 dm7 dq56 to dq63 dqs5 /dqs5 dm5 dq40 to dq47 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 ck1 ck0 cke1 cke0 odt1 odt0 /ck1 /ck0 /cs1 3 18 /cs0 address, ba command d9 d10 d11 d7 d6 d5 d4 d15 d14 d13 d12 /reset /reset:sdrams (d0 to d15) vddspd spd vrefdq sdrams (d0 to d15) vtt vrefca sdrams (d0 to d15) vdd sdrams (d0 to d15) vss sdrams (d0 to d15), spd notes : 1. dq wiring may be changed within a byte. 2. dq, dqs, /dqs, odt, dm, cke, /cs relationships must be maintained as shown. * d0 to d15: 2g bits ddr3 sdram address, ba: a0 to a14, ba0 to ba2 command: /ras, /cas, /we u1: 256 bytes eeprom rs1: 15 ? rs2: 36 ? rs3: 30 ? rs4: 240 ? zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck rs1 rs1 rs1 rs1 rs1 rs2 rs2 rs2 rs2 rs2 rs3 rs3 rs2 rs2 rs2 rs2 rs2 rs3 rs3 rs1 rs1 rs1 rs1 rs1 rs1 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs4 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 vtt d0 d9 d10 d11 d4 d15 d6 d5 d3 d2 d1 d8 d7 d12 d13 d14 v1 v8 v8 v6 v6 v7 v7 v2 v2 v4 v4 v3 v3 v1v9 v9 v5 v5 /dqs dm dq0 to dq7 d8 zq /cs address ba command odt cke ck /ck d2 dqs zq /dqs dm dq0 to dq7 /cs address ba command odt cke ck /ck dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 dqs /dqs dm dq0 to dq7 zq /cs address ba command odt cke ck /ck zq /cs address ba odt cke ck /ck zq /cs address ba command odt cke ck /ck d0 d1 d3 command dqs address and control lines a2 serial pd sda a0 a1 scl sa0 sa1 sda scl u0 wp
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 13 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit notes power supply voltage vdd ? 0.4 to +1.975 v 1, 3, 4 input voltage vin ? 0.4 to +1.975 v 1, 4 output voltage vout ? 0.4 to +1.975 v 1, 4 reference voltage vrefca ? 0.4 to 0.6 vdd v 3, 4 reference voltage for dq vrefdq ? 0.4 to 0.6 vddq v 3, 4 storage temperature tstg ? 55 to +100 c 1, 2, 4 power dissipation pd 8 w short circuit output current iout 50 ma 1, 4 notes: 1. stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only and func tional operation of the device at these or any other conditions above those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface te mperature on the center/t op side of the dram. 3. vdd and vddq must be within 300m v of each other at all times; and vref must be not greater than 0.6 vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. 4. ddr3 sdram component specification. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature condition parameter symbol rating unit notes operating case temperature tc 0 to +95 c 1, 2, 3 notes: 1. operating tem perature is the case surface temperat ure on the center/top side of the dram. 2. the normal temperature range specifies the temp eratures where all dram specifications will be supported. during operati on, the dram case temperature must be maintained between 0c to +85c under all operating conditions. 3. some applications require operation of the dram in the exte nded temperature range between +85c and +95c case temperature. full spec ifications are guaranteed in this r ange, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9s. (this double refresh requirement may not apply for some devices.) b) if self-refresh operation is required in the extend ed temperature range, t hen it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 bit [a6, a7] = [0, 1]) or enable the optional auto se lf-refresh mode (mr2 bit [a6, a7] = [1, 0]).
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 14 recommended dc operating conditions (tc = 0c to +85c) parameter symbol min. typ. max. unit notes supply voltage vdd, vddq 1.425 1.5 1.575 v 1, 2, 3 vss 0 0 0 v 1 vddspd 3.0 3.3 3.6 v input reference voltage vrefca (dc) 0.49 vddq 0.50 vddq 0.51 vddq v 1, 4, 5 input reference voltage for dq vrefdq (dc) 0.49 vddq 0.50 vddq 0.51 vddq v 1, 4, 5 termination voltage vtt vddq/2 ? tbd tbd vddq/2 + tbd v notes: 1. ddr3 sdram co mponent specification. 2. under all conditions vddq must be less than or equal to vdd. 3. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 4. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than 1% vdd (for reference: approx 15 mv). 5. for reference: approx. vdd/2 15 mv.
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 15 dc characteristics 1 (tc = 0c to +85c, vdd = 1.5v 0.075v, vss = 0v) parameter symbol data rate (mbps) max. unit notes operating current (act-pre) (another rank is in idd2p1) idd0 1600 1333 1066 tbd 880 800 ma operating current (act-pre) (another rank is in idd3n) idd0 1600 1333 1066 tbd 1080 856 ma operating current (act-read-pre) (another rank is in idd2p1) idd1 1600 1333 1066 tbd 1000 920 ma operating current (act-read-pre) (another rank is in idd3n) idd1 1600 1333 1066 tbd 1200 976 ma idd2p1 1600 1333 1066 tbd 560 480 ma fast pd exit precharge power-down standby current idd2p0 1600 1333 1066 tbd 240 240 ma slow pd exit precharge standby current idd2n 1600 1333 1066 tbd 720 720 ma precharge standby odt current idd2nt 1600 1333 1066 tbd 720 720 ma precharge quiet standby current idd2q 1600 1333 1066 tbd 720 640 ma active power-down current (always fast exit) idd3p 1600 1333 1066 tbd 592 592 ma active standby current idd3n 1600 1333 1066 tbd 960 880 ma operating current (burst read operating) (another rank is in idd2p1) idd4r 1600 1333 1066 tbd 1520 1320 ma operating current (burst read operating) (another rank is in idd3n) idd4r 1600 1333 1066 tbd 1720 1520 ma operating current (burst write operating) (another rank is in idd2p1) idd4w 1600 1333 1066 tbd 1560 1360 ma operating current (burst write operating) (another rank is in idd3n) idd4w 1600 1333 1066 tbd 1760 1560 ma burst refresh current (another rank is in idd2p1) idd5b 1600 1333 1066 tbd 2440 2360 ma burst refresh current (another rank is in idd3n) idd5b 1600 1333 1066 tbd 2640 2560 ma all bank interleave read current (another rank is in idd2p1) idd7 1600 1333 1066 tbd 2520 2080 ma all bank interleave read current (another rank is in idd3n) idd7 1600 1333 1066 tbd 2720 2280 ma
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 16 self-refresh current (tc = 0 c to +85 c, vdd = 1.5v 0.075v) parameter symbol max. unit notes self-refresh current normal temperature range idd6 272 ma self-refresh current extended temperature range idd6et 352 ma auto self-refresh current (optional) idd6tc ? ma timings used for idd and iddq measurement-loop patterns ddr3-1600 ddr3-1333 ddr3-1066 parameter 11-11-11 9-9-9 7-7-7 unit cl tbd 9 7 nck tck min. tbd 1.5 1.875 ns nrcd min. tbd 9 7 nck nrc min. tbd 33 27 nck nras min. tbd 24 20 nck nrp min. tbd 9 7 nck nfaw tbd 20 20 nck nrrd tbd 4 4 nck nrfc tbd 107 86 nck
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 17 pin functions ck, /ck (input pin) ck and /ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). /cs (input pin) all commands are masked when /cs is registered high. /cs provides for external rank selection on systems with multiple ranks. /cs is considered part of the command code. /ras, /cas, and /we (input pins) /ras, /cas and /we (along with /cs) define the command being entered. a0 to a14 (input pins) provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10(ap) and a12(/bc) have additional functions, see below) the address inputs also provide t he op-code during mode register set commands. [address pins table] address (a0 to a14) row address (ra) column address (ca) notes ax0 to ax14 ay0 to ay9 a10(ap) (input pin) a10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (h igh: auto-precharge; low: no auto-precharge) a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 = low) or all banks (a10 = high). if only one bank is to be prec harged, the bank is selected by bank addresses (ba). a12 (/bc) (input pin) a12 is sampled during read and write commands to determi ne if burst chop (on-the-fly) will be performed. (a12 = high: no burst chop, a12 = low: burst chopped.) ba0 to ba2 (input pins) ba0, ba1 and ba2 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determine if a mode register is to be accessed during a mrs cycle. [bank select signal table] ba0 ba1 ba2 bank 0 l l l bank 1 h l l bank 2 l h l bank 3 h h l bank 4 l l h bank 5 h l h bank 6 l h h bank 7 h h h remark: h: vih. l: vil.
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 18 cke (input pin) cke high activates, and cke low deactivates, internal cl ock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refr esh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self -refresh exit. after vref has become stable during the power-on and initialization sequence, it must be maintained for proper operat ion of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power-down. input buffers, excluding cke, are disabled during self-refresh. dq (input and output pins) bi-directional data bus. dqs and /dqs (input and output pin) output with read data, input with write data. edge- aligned with read data, centered in write data. the data strobe dqs is paired with differential signals /dqs to provide differential pair signaling to the system during reads and writes. odt (input pins) odt (registered high) enables termination resistance inter nal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, /dqs, dm. the odt pin will be ignored if the mode register (mr1) is programmed to disable odt. dm (input pins) dm is the reference signal of the dat a input mask function. dms are sampl ed at the cross point of dqs and /dqs. vdd (power supply pins) 1.5v is applied. (vdd is for the internal circuit.) vddspd (power supply pin) 3.3v is applied (for serial eeprom). vss (power supply pin) ground is connected. vtt (power supply pin) i/o termination supply for sdram. vrefdq (power supply) reference voltage for dq. vrefca (power supply) reference voltage for ca. /reset (input pin) /reset is negative active signal (active low) and is referred to gnd. detailed operation part, electrical characteristics and timing waveforms refer to the edj2104base, edj2108base datasheet (e1505e).
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 19 physical outline 67.60 9.00 21.15 2.15 39.00 2.45 2.15 2.45 21.00 30.00 1 2 unit: mm 1.00 0.10 4.00 min 4.00 3.80 max (datum -a-) 4x full r component area (back) eca-ts2-0215-01 b a c 3.00 1.65 detail b detail a 0.35 max 2.55 min 4.00 0.10 0.60 0.45 0.03 1.00 0.10 detail c full r 3.00 1.35 detail d front side back side 20.00 d 6.00 63.60 2.00 min 203 (datum -a-) component area (front) 0.2 max 0.35 max contact pad 204
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 20 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
ebj41uf8bas0 preliminary data sheet e1545e20 (ver. 2.0) 21 m01e0706 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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